A wide range of electronics packaging technologies have been developed for semiconductor devices to meet the varied needs of different applications. Over time semiconductor dimensions have decreased and pin counts have increased. Additionally, there is a growing need to support a wider range of operating currents at both high and low current levels. Packaging technology has had difficulty meeting these needs.
The package has a large impact on performance, size, price and reliability of the product. The flip-chip technique has been developed in response to a range of these needs. In the flip chip approach, the chips are fabricated with contacts on the top surface and then flipped over for attachment of those contacts to conductive traces on a substrate (e.g., a circuit board) or in a package. This approach has the advantage of eliminating wire bonding, but has a number of challenges in terms of process complexity and cost because it requires a complicated solder-based connection process, including solder bump formation, chip to board alignment, reflow, flux removal, underfill, and cure processes. Moreover, flip-chip processes are generally performed on individual singulated devices, and thus uniformity and repeatability are often problematic.
In view of the foregoing, there is a need for a more uniform and less complex flip-chip-based packaging process for electronic devices batch processed on semiconductor substrates.